Pano logic G2 Reverse Engineering

I have begun to look into the Pano G2 DVI client and getting some code into the FPGA.  To do this I first tore the unit down. It is nearly identical construction to the G1 client. 

Pano G2  client board.

I was able to find that the jtag connector P1 looks identical to the G1 client Jtag connector.  I assumed that the designers would keep the same pinout and I was correct. Using the pinout below and some crufty wire-wrapping I could connect my Xilinx platform cable to the board. Thanks to:

P2 is jtag and its pins are ( pin1 nearest to P2 silk):

  1. vcc
  2. tdi
  3. tms
  4. tdo
  5. tck
  6. gnd
Note P2 and dot to designate pin 1 of P2

I then used an older version of ISE ( 14.4)  for windows that I knw could talk with my USB platform cable.  I was able to see the Jtag chain and the XC6slx150 device.

Next , I looked at the Chip id and the DNA  to make sure I can read stuff. and sure enough I can see the device.

Next up is finding the IO pin for the clock oscillator and the  LED on the board.  So I can blink it with my hello world bit strream.

And connecting to the 14.7 VM based ISE so I can program the bit stream  from the version of ISE that can make xc6slx150 bit files.  

Update: 2/18/2019

The above work was done on a windows 10 machine with a xilinx DLC9G platform cable.  I wanted to use my older windows 7 dev machine but had several issues with getting the stuff to work.  

1)The Xilinx ISE container did not find the License file and would not run Implementation or bit stream generation for large devices like the lx150. The solution was that the  license file in the container has the MACADDRESS  that the original windows10 pc container was installed on.  I spoofed the ethernet MAC  in virtualbox to match the windows 10 id and now it works…

2)The xilinx platform cable was never recognized. I fought with this for quite a while.  I ended up reloading the platform cable drivers, that did not seem to help. then I …  forgot what I did… it will come to me…. someday…